In recent years, power reduction technology for logic IC (integrated circuit) has been studied and developed. To get a low power consumption IC, a circuit configuration to which power is selectively supplied to circuit blocks has been employed. More specifically, power is supplied to the circuit blocks which need power to perform a task and not supplied to other circuit blocks which do not perform the task.
However, conventional logic simulators request a circuit description which represents every circuit block of the logic circuit operating under the supply of power. Therefore, the conventional logic simulators cannot handle the circuit description for a logic circuit to which power is selectively supplied to circuit blocks of the logic circuit and described with cell descriptions retrieved from cell libraries for IC design using commercial CAD tools. In order to simulate the circuit configuration using the conventional simulator, the logic circuit is required to be classified into small circuit blocks, for example, a power supply circuit block and logic circuit blocks, and each circuit block is needed to be simulated separately under different conditions. Then, all executed simulation results are collected to consider a total power consumption of the IC circuit. When the conventional simulator is used for design verification, additional manual labor may be needed to adjust connections between the circuit blocks and functional simulations are needed to perform for the individual circuit block. Consequently, it become very complicated to get the total simulation result and a lot of additional efforts are needed.
There has been proposed one technique which recreates a cell library by adding power terminals to all cells. However, it requires a lot of additional work to prepare new cells manually and maintain the additional new cell library besides the cell library which is commonly used for the IC design. Moreover, the processes used to add terminals to the cells and to connect the circuit blocks are not able to be implemented in RTL (register transfer level) design methodology, which is commonly used in IC design, but are instead only implemented in a gate level design methodology.